In conventional multi-bit cascaded sigma-delta A/D converters it is known that the resolution can be extended for several bits by providing a subtraction and gain stage in between cascaded sigma-delta loops. However, in the known two-phase switched capacitor implementations, the inputs to the gain stage must normally be valid on the same clock phase.
For example, Walden et. al in a paper entitled "Architectures for High-Order Multibit Sigma-Delta Modulators", Proceedings 1990 ISCAS, pp. 885-898, discloses such a previously-known device. In such devices as seen in this reference, in order to generate the inter-loop error signal the input and loop integrator amplifier output are required to be in phase. This in turn has heretofore required the use of a non-delaying integrator in the sigma-delta loops.
It has been found that, in analog-to-digital converters utilizing cascaded Sigma-Delta loops, the use of the known integrator circuits introduces problems in relation to pole error, settling accuracy, and higher gain-bandwidth requirements for the operational amplifiers.
It is therefore an object of the invention to provide a multi-bit cascaded sigma-delta analog-to-digital converter having higher resolution (number of bits), higher sample rate, and lower harmonic distortion than previous multi-bit cascaded sigma-delta approaches.
It is another object of the invention to provide a multi-bit cascaded sigma-delta A/D converter using delaying switched capacitor integrators.
It is yet another object of the invention to relax settling time requirements and to thereby ease operational amplifier (op amp) design constraints for multi-bit cascaded sigma-delta A/D converters.
It is still another object of the invention to provide a cascaded sigma-delta A/D converter wherein there is a true sample and hold input; the op amp amplifies a fixed amount of charge; nodes are settled utilizing the dc gain of the op amp (much higher than the high frequency gain) thus permitting greater settling accuracy.